1. Field
Example embodiments of the inventive concepts relate to semiconductor devices and methods of manufacturing the same. More particularly, example embodiments relate to semiconductor devices having shallow trench isolation (STI) structures and methods of manufacturing the same.
2. Description of the Related Art
Isolation layers may be formed in semiconductor devices by a shallow trench isolation (STI) process. When a STI process is performed, a pad oxide layer and a pad nitride layer pattern may be formed on a silicon substrate. A trench may be formed in an upper portion of the substrate by etching the substrate using the pad nitride layer pattern as an etch mask. An oxide layer may be formed to fill the trench on the substrate. An upper portion of the oxide layer may be planarized by a chemical mechanical polishing (CMP) process and/or an etch back process, thereby forming an isolation layer having a STI structure in the trench.
Prior to forming an oxide layer in the trench, an inner wall of the trench may be thermally treated to form an inner wall oxide layer that may cure damage to the substrate generated during the etch process. The isolation layer may expand in subsequent heat treatments (e.g., during forming of a gate oxide layer) thereby generating dislocation of silicon in the substrate.
The pad nitride layer pattern may be removed by a wet etch process. During the wet etch, upper edge portions of the isolation layer and the substrate may be removed to form a dent (e.g., a recess). A gate oxide layer subsequently formed on the substrate may be relatively thin at the upper edge portion of the substrate. Thus, the electric field may be concentrated at the upper edge portion to generate an inverse narrow width effect in which a threshold voltage of a transistor may increase as a channel width decreases. Additionally, a hump effect may occur in which a threshold voltage decreases at a portion of a channel of a transistor because silicon at the upper edge portion of the substrate may not have a uniform crystalline structure.
In order to solve the above problems, a nitride liner may be formed on the inner wall oxide layer. The nitride liner may absorb stress on the substrate because of the expansion of the isolation layer in a subsequent oxidation process and may reduce and/or prevent penetration of oxygen into the inner wall oxide layer, thereby reducing and/or preventing the dislocation of silicon in the substrate. The double liner structure having both of the inner wall oxide layer and the nitride liner may reduce a change of a threshold voltage. However, the double liner may deteriorate gap filling characteristics and the process for forming the above STI structure may be complicated.